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# Sequential Circuits – II

Sequential Circuits â€“ II

Contents

Define and classify Counters 2

Construct Two-bit Ripple Up-Counter and Down Counter 3

Construct Two-bit Ripple Up/Down Counter 4

Design Mod-6 Asynchronous Counter 5

Design Mod-10 Asynchronous Counter 6

Recall the Effect of Propagation Delay in Ripple Counters 7

Design Ring Counter 8

Design Johnson Counter 9

Design Synchronous BCD Counter 11

Design 3-bit Synchronous Up-Counter 13

Design 3-bit Synchronous Down-Counter 16

Design 3-bit Synchronous Up/Down Counter 18

Design MOD-6 Synchronous Counter 20

Design MOD-9 Synchronous Counter 23

Recall Finite State Machine 25

Describe: 1. Moore Machine 2. Mealy Machine 26

Describe Moore Machine 29

Describe Mealy Machine 30

Describe Minimization of Sequential Machine 32

Recall State Reduction Methods: Successive Partitioning 36

Recall State Reduction Methods: Implication Chart 36

Describe Method of State Assignment 37

Recall Hazards and Its types 38

Differentiate between Static and Dynamic Hazards 39

Determine Hazards in Combinational Circuits 39

Recall Faults and its types 40

Differentiate between Struck-At and Bridging Faults 41

Differentiate between Single Stuck-At and Multiple Stuck-At Faults 41

Describe Faults Detection in Combinational and Sequential circuits 42

# Define and classify Counters

Counters are digital circuits that are used to count the number of events that occur over time. They are commonly used in applications such as frequency measurement, timekeeping, and control systems.

Counters can be classified into several categories based on their characteristics:

1. Asynchronous or Ripple Counters: These are the simplest type of counters and use flip-flops that are triggered by the output of the preceding stage. The output of each stage serves as a clock input to the next stage, resulting in a ripple effect as the count progresses. Asynchronous counters are simple to implement but can be slow and prone to glitches.
2. Synchronous Counters: These counters use a common clock signal to trigger all stages simultaneously. This results in a faster and more reliable count than asynchronous counters, but they require more complex circuitry.
3. Up Counters: These counters count up from a starting value, typically zero. They are the most common type of counter and can be implemented using either asynchronous or synchronous techniques.
4. Down Counters: These counters count down from a starting value, typically a preset value. They can also be implemented using either asynchronous or synchronous techniques.
5. Bidirectional Counters: These counters can count up or down based on a control signal. They are commonly used in applications where the count needs to change direction based on some external condition.
6. Ring Counters: These counters use a circular shift register to produce a sequence of output states. The count is determined by the number of stages in the shift register.
7. Johnson Counters: These counters are a variation of the ring counter, where the output sequence is complemented at each stage. This results in a sequence that repeats after 2n-1 states, where n is the number of stages in the counter.

Counters can also be classified based on their applications. For example, event counters count the number of events that occur in a system, while frequency counters measure the frequency of a signal. Time interval counters measure the time between two events, and programmable counters can be configured to count in different ways based on the input configuration.

Overall, counters are a fundamental building block in digital electronics, and their wide range of applications and configurations make them essential for many different types of digital systems.

# Construct Two-bit Ripple Up-Counter and Down Counter

Sure, here are the designs for a 2-bit ripple up-counter and down counter using D flip-flops: Two-bit Ripple Up-Counter:

The truth table for a 2-bit ripple up-counter is:

 Q1 Q0 Count 0 0 0 0 1 1 1 0 2 1 1 3

# Construct Two-bit Ripple Up/Down Counter

Sure, here’s the design for a 2-bit ripple up/down counter using D flip-flops:

Two-bit Ripple Up/Down Counter:

The truth table for a 2-bit ripple up/down counter is:

 Q1 Q0 Count 0 0 0 0 1 1 1 0 2 1 1 3

# Design Mod-6 Asynchronous Counter

Sure, here’s the design for a mod-6 asynchronous counter using J-K flip-flops:

Mod-6 Asynchronous Counter:

The truth table for a mod-6 asynchronous counter is:

 Q2 Q1 Q0 Count 0 0 0 0 0 0 1 1 0 1 0 2

# Design Mod-10 Asynchronous Counter

A Mod-10 Asynchronous Counter can be designed using a combination of a Mod-2 counter and a Mod-5 counter. The Mod-2 counter can be implemented using a simple toggle flip-flop, while the Mod-5 counter can be implemented using a 3-bit ripple counter.

The following steps can be followed to design the Mod-10 Asynchronous Counter:

1. Design the Mod-2 Counter:
• Implement a toggle flip-flop using a D flip-flop and connect its Q output to its D input. This will give a 2-bit binary sequence of 0-1-0-1… at the output.
2. Design the Mod-5 Counter:
• Implement a 3-bit ripple counter using D flip-flops. This counter will give a 3-bit binary sequence of 0-1-2-3-4-0-1-2-3-4… at the output.
• The counter will need to reset to 0 after the count of 4.
3. Combine the Mod-2 and Mod-5 Counters:
• Connect the output of the Mod-2 counter to the clock input of the Mod-5 counter.
• The Mod-5 counter will increment by 1 each time the Mod-2 counter outputs a 1, resulting in a Mod-10 count sequence of 0-1-2-3-4-5-6-7-8-9-0-1-2-3-4…

Therefore, a Mod-10 Asynchronous Counter can be designed using a Mod-2 counter and a Mod-5 counter connected in series.

# Recall the Effect of Propagation Delay in Ripple Counters

Propagation delay is a delay that occurs when a signal passes through a digital circuit. In ripple counters, such as the ripple up-counter and ripple down-counter, the output of each flip-flop is connected to the clock input of the next flip-flop.

When a clock pulse is applied, the first flip-flop in the chain toggles its output, which causes the next flip-flop to toggle after a certain amount of propagation delay. This delay is due to the time required for the signal to propagate through the interconnects and logic gates between the two flip-flops. As a result, the output of the second flip-flop changes slightly after the output of the first flip-flop changes.

This delay is propagated through the chain, causing a delay between the toggling of each flip-flop. The propagation delay can cause errors in the count sequence of the ripple counter, especially at high clock frequencies. This effect is known as the ripple carry or ripple propagation delay, and it can limit the maximum operating frequency and accuracy of the counter. Therefore, ripple counters are not suitable for high-speed applications that require precise counting.

# Design Ring Counter

A ring counter is a type of counter where the output of the last flip-flop is connected to the input of the first flip-flop, forming a ring. The ring counter is shifted left or right by pulsing the clock input of the first flip-flop.

Here is a design of a 4-bit ring counter:

First, we need to design a D flip-flop with an enable input. The enable input will allow us to control when the flip-flop can be toggled.

We need four of these D flip-flops to enable us to form a 4-bit ring counter. We connect the output of the last flip-flop to the input of the first flip-flop, forming a ring.

To shift the ring counter left or right, we need to pulse the clock input of the first flip-flop. To shift the ring counter left, we need to connect the clock input of the first flip-flop to the output of the fourth flip-flop. To shift the ring counter right, we need to connect the clock input of the first flip-flop to the output of the second flip-flop.

To make the ring counter count, we need to connect the enable input of each flip-flop to the output of the previous flip-flop. For example, the enable input of the second flip-flop is connected to the output of the first flip-flop, and so on. The enable input of the first flip-flop is connected to the output of the fourth flip-flop. This configuration creates a pattern of ones that rotates around the ring.

# Design Johnson Counter

Definition: It is also known as a modified ring counter. It is designed with a group of flip-flops, where the inverted output from the last flip-flop is connected to the input of the first flip-flop. Generally, it is implemented by using D flip-flops or JK flip-flops. It is also known as an inverse feedback counter or twisted ring counter. This follows the sequence of bit patterns. When compared to the ring counter, it uses only half of the number of flip-flops. So, the MOD will be 2n, if there are n flip-flops.

Circuit Diagram

The johnson counter circuit diagram is the cascaded arrangement of â€˜nâ€™ flip-flops. In such design, the output of the proceeding flip-flop is fed back as input to the next flip-flop. For example, the inverted output of the last flip-flop â€˜QÌ…nâ€™ is fed back to the first flip-flop in the sequence bit pattern. The counter registers cycles in a closed-loop i.e circulates within the circuit.

Consider the 4-bit Johnson counter, it contains 4 D flip-flops, which is called 4-bit Johnson counter. It has preset and clear pins to initialize or start and reset the counted.

Reset pin acts as an on/off switch. So, the flip-flops can be enabled by clicking the Reset switch.

CLK pin is used to observe the changes in the output of the flip-flops.

Standard 2,3 and 4 stages johnson counters are used to divide the frequency of clock signals with the help of varying feedback connections. For example, a 3-stage johnson counter can be used as a 3-phase and 120 degrees phase shift square wave generator. 5-stage Johnson counter is used as a synchronous decade counter (CD4017) or divider circuit. 2-stage acts as a quadrature oscillator or generator that produces individual output signals of 90 degrees each concerning the input signal.

Truth Table

Consider the truth table of the 3-bit Johnson counter. The output of the proceeding flip-flop is connected as the input of the next flip-flop. The clock signal(CLK) is used to know the changes in the output. It contains 3 flip-flops, Q0, Q1, Q2 are the outputs of the flip-flops. The counter counts the state of cycles in a continuous closed loop.

# Design Synchronous BCD Counter

A synchronous BCD counter is a counter that counts from 0 to 9 in binary-coded decimal (BCD) format. It can be designed using flip-flops and combinational logic.

The circuit diagram for a synchronous BCD counter using J-K flip-flops is shown below:

The counter consists of four J-K flip-flops (FF0, FF1, FF2, and FF3) and a combinational logic circuit that generates the next state. Each flip-flop represents a decimal digit in the BCD code.

The J-K flip-flops are connected such that the output of each flip-flop is connected to the clock input of the next flip-flop. The clock input of the first flip-flop (FF0) is connected to the input clock signal.

The combinational logic circuit consists of a series of AND gates and an OR gate. The inputs to the AND gates are the outputs of the flip-flops and the complemented outputs of the flip-flops. The outputs of the AND gates are connected to the inputs of the OR gate. The output of the OR gate is used as the next state input to the flip-flops.

The truth table for the combinational logic circuit is shown below:

Inputs | Outputs

————————

Q3 Q2 Q1 Q0 | Q3+ Q2+ Q1+ Q0+

————————

0 0 0 0 | 0 0 0 1

0 0 0 1 | 0 0 1 0

0 0 1 0 | 0 0 1 1

0 0 1 1 | 0 1 0 0

0 1 0 0 | 0 1 0 1

0 1 0 1 | 0 1 1 0

0 1 1 0 | 0 1 1 1

0 1 1 1 | 1 0 0 0

1 0 0 0 | 1 0 0 1

The circuit works as follows:

1. At the beginning, all flip-flop outputs are set to 0.
2. When the clock input is high, the combinational logic circuit generates the next state based on the current state of the flip-flops.
3. The next state is then loaded into the flip-flops on the rising edge of the clock signal.
4. The counter then counts up from 0 to 9 in BCD format, and then resets to 0 and starts over again.

Note that this is a 4-bit synchronous BCD counter, so it counts from 0 to 9. For larger counters, more flip-flops and additional logic would be needed.

# Design 3-bit Synchronous Up-Counter

A 3-bit synchronous up-counter can be designed using J-K flip-flops and combinational logic. The counter counts from 0 to 7 in binary (000 to 111) and then resets to 0 and starts over again.

The circuit diagram for a 3-bit synchronous up-counter using J-K flip-flops is shown below:

The counter consists of three J-K flip-flops (FF0, FF1, and FF2) and a combinational logic circuit that generates the next state. Each flip-flop represents a bit in the binary count.

The J-K flip-flops are connected such that the output of each flip-flop is connected to the clock input of the next flip-flop. The clock input of the first flip-flop (FF0) is connected to the input clock signal.

The combinational logic circuit consists of a series of AND gates and an OR gate. The inputs to the AND gates are the outputs of the flip-flops and the complemented outputs of the flip-flops. The outputs of the AND gates are connected to the inputs of the OR gate. The output of the OR gate is used as the next state input to the flip-flops.

The truth table for the combinational logic circuit is shown below:
Inputs | Outputs

————————

Q2 Q1 Q0 | Q2+ Q1+ Q0+

————————

0 0 0 | 0 0 1

0 0 1 | 0 1 0

0 1 0 | 0 1 1

0 1 1 | 1 0 0

1 0 0 | 1 0 1

1 0 1 | 1 1 0

1 1 0 | 1 1 1

1 1 1 | 0 0 0

The circuit works as follows:

1. At the beginning, all flip-flop outputs are set to 0.
2. When the clock input is high, the combinational logic circuit generates the next state based on the current state of the flip-flops.
3. The next state is then loaded into the flip-flops on the rising edge of the clock signal.
4. The counter then counts up from 0 to 7 in binary, and then resets to 0 and starts over again.

Note that this is a 3-bit synchronous up-counter, so it counts from 0 to 7. For larger counters, more flip-flops and additional logic would be needed.

# Design 3-bit Synchronous Down-Counter

A 3-bit synchronous down-counter can be designed using J-K flip-flops and combinational logic. The counter counts from 7 to 0 in binary (111 to 000) and then resets to 7 and starts over again.

The circuit diagram for a 3-bit synchronous down-counter using J-K flip-flops is shown below:

The counter consists of three J-K flip-flops (FF0, FF1, and FF2) and a combinational logic circuit that generates the next state. Each flip-flop represents a bit in the binary count.

The J-K flip-flops are connected such that the output of each flip-flop is connected to the clock input of the next flip-flop. The clock input of the first flip-flop (FF0) is connected to the input clock signal.

The combinational logic circuit consists of a series of AND gates and an OR gate. The inputs to the AND gates are the outputs of the flip-flops and the complemented outputs of the flip-flops. The outputs of the AND gates are connected to the inputs of the OR gate. The output of the OR gate is used as the next state input to the flip-flops.

The truth table for the combinational logic circuit is shown below:

Inputs | Outputs

————————

Q2 Q1 Q0 | Q2- Q1- Q0-

————————

1 1 1 | 1 1 0

1 1 0 | 1 0 1

1 0 1 | 1 0 0

1 0 0 | 0 1 1

0 1 1 | 0 1 0

0 1 0 | 0 0 1

0 0 1 | 0 0 0

0 0 0 | 1 1 1

The circuit works as follows:

1. At the beginning, all flip-flop outputs are set to 1.
2. When the clock input is high, the combinational logic circuit generates the next state based on the current state of the flip-flops.
3. The next state is then loaded into the flip-flops on the rising edge of the clock signal.
4. The counter then counts down from 7 to 0 in binary, and then resets to 7 and starts over again.

Note that this is a 3-bit synchronous down-counter, so it counts from 7 to 0. For larger counters, more flip-flops and additional logic would be needed.

# Design 3-bit Synchronous Up/Down Counter

A 3-bit synchronous up/down counter can be designed using J-K flip-flops and combinational logic. The counter can count both up and down, depending on the state of the control input. The circuit diagram for a 3-bit synchronous up/down counter using J-K flip-flops is shown below:

The counter consists of three J-K flip-flops (FF0, FF1, and FF2), a control input (UP/DN), and a combinational logic circuit that generates the next state. Each flip-flop represents a bit in the binary count.

The J-K flip-flops are connected such that the output of each flip-flop is connected to the clock input of the next flip-flop. The clock input of the first flip-flop (FF0) is connected to the input clock signal.

The control input (UP/DN) is connected to the input of an inverter. The output of the inverter is connected to one input of an AND gate, with the other input connected to the clock input of the flip-flops.

The combinational logic circuit consists of a series of AND gates and an OR gate. The inputs to the AND gates are the outputs of the flip-flops and the complemented outputs of the flip-flops, as well as the control input and the complemented control input. The outputs of the AND gates are connected to the inputs of the OR gate. The output of the OR gate is used as the next state input to the flip-flops.

The truth table for the combinational logic circuit is shown below:

Inputs | Outputs

————————————

UP/DN Q2 Q1 Q0 | Q2+ Q1+ Q0+ Q2- Q1- Q0-

————————————

0 1 1 1 | 0 0 0 1 1 0

0 1 1 0 | 0 0 1 1 0 1

0 1 0 1 | 0 0 1 1 0 0

0 1 0 0 | 0 1 0 0 1 1

0 0 1 1 | 0 1 0 0 1 0

0 0 1 0 | 0 1 1 0 0 1

0 0 0 1 | 0 1 1 0 0 0

0 0 0 0 | 1 1 1 0 1 1

1 1 1 1 | 1 1 1 0 0 0

1 1 1 0 | 1 1 0 0 1 1

1 1 0 1 | 1 1 0 0 1 0

1 1 0 0 | 1 0 1 1 0 1

# Design MOD-6 Synchronous Counter

1. A MOD-6 synchronous counter can be designed using a 3-bit binary counter with a combinational circuit that resets the counter to zero after the count of 6.
2. The truth table for the MOD-6 counter is as follows:

Using the truth table, we can design the combinational circuit that generates the next count based on the current count.

The circuit for the MOD-6 synchronous counter using a 3-bit binary counter is shown below:

To design a MOD-6 synchronous counter using a 3-bit binary counter, we need to create a circuit that counts from 0 to 5 (MOD-6). The 3-bit binary counter can be constructed using flip-flops, and additional logic gates can be used to implement the MOD-6 behavior.

To design a MOD-6 synchronous counter using D flip-flops, we need a circuit that counts from 0 to 5 (MOD-6). Each D flip-flop will represent one bit of the counter.

Here’s the circuit diagram for a MOD-6 synchronous counter using D flip-flops: